1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device for performing a refresh operation.
2. Description of the Related Art
As well-known in the art, a semiconductor device includes a memory cell having one transistor and one capacitor. Data is stored by charging a charge on the capacitor. Since a leakage current occurs in the capacitor, the charge stored on the capacitor is subject to loss without recharging. The semiconductor device should perform a refresh operation to maintain the charge stored on the capacitor.
More specifically, in the semiconductor device, a high electric potential is applied to the memory cell when data of ‘1’ is to be stored therein and a low electric potential is applied to the memory cell when data of ‘0’ is to be stored therein. The capacitor constituting the memory cell is designed in such manner that an electric charge therein should be always maintained in an ideal memory cell when there is no electrical change. In fact, however, the capacitor loses the electric charge stored therein in the form of a leakage current as time goes by, which means the electric charge stored therein may not be maintained and makes it impossible to identify whether the stored data is ‘1’ or ‘0’. Therefore, it is necessary to perform a series of processes that periodically senses data stored in each memory cell and again restores it therein in order to maintain data in the memory cell. This series of processes is called the refresh operation.
FIG. 1 is a circuit diagram illustrating a conventional refresh signal generator.
Referring to FIG. 1, a refresh signal AFACT for generating a refresh command RE is generated by logically combining a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE, which are external signals inputted from outside.
The refresh signal generator generate the refresh signal AFACT of a logic high in response to the chip select signal CS of the logic high, the row address strobe signal RAS of the logic high, the column address strobe signal CAS of the logic high and the write enable signal WE of a logic low.
A semiconductor device, during a refresh operation mode, sequentially changes an internal address and may enable word lines according the internal address in response to an external command, e.g., the refresh signal AFACT as shown in FIG. 1. During the refresh operation mode according to the external command, a row address is sequentially increased at a predetermined period and a corresponding word line of the memory cell is selected. A charge stored in the memory cell of the enabled word line is sensed, amplified, and re-stored. Through the refresh operation, the data stored in the memory cell maintains without loss.
A target row refresh (TRR) operation is to prevent data loss of adjacent memory cells, which may be caused by excessive activation of a word line. During the TRR operation, an active and precharge operation for adjacent word lines as well as a target word line is performed. Through the TRR operation, the adjacent memory cell may be secured even though the excessive activation of the target word line.
However, in order for a redundancy word line to be activated and precharged as the target word line during the TRR operation, a circuit for the TRR operation to the redundancy word line needs to be complicated and more space for the circuit may be required, which makes it hard to reduce size of the semiconductor device and fabricating cost of the semiconductor device.